(1) Field of the Invention
The invention relates to reticle options in a semiconductor device, and more particularly, to a method of detecting reticle option layers in an integrated circuit device.
(2) Description of the Prior Art
During the early stages of product development, it is important to get test data based on actual silicon as soon as possible. One way to expedite this data availability on a new product is to include several chip layer versions on the same reticle. So, depending on the number of chip pattern placements within the reticle, there can be up to that number of layer versions on the reticle. The most promising of the layer versions, based on test results, could then be selected and implemented as a single version for the production reticle.
To facilitate testing and evaluation of the integrated circuit, a means of easily identify layer versions is needed. Ideally, such versions should be identified electrically either by directly probing the die or by probing individual pins of packaged circuit. The only known prior art approach to provide electrical identification of a layer version is through the use of existing redundancy or chip identification fuses that are either connected or disconnected based on a metal layer version. However, this approach is limited in terms of the layers that can be used as reticle versions.
Several prior art approaches relate to reticle layers, identification, and related methods. U.S. Pat. No. 5,940,704 to Takeuchi discloses a method of making a reference apparatus for determining current or voltage in nonvolatile memory cells. The reference apparatus comprises cells with different threshold voltages due to differences in the floating gate to control gate coupling ratios. The current in the nonvolatile cell is compared to that in the reference cells using a sense amplifier. U.S. Pat. No. 5,747,868 to Reddy et al teaches a method to form polysilicon laser fusible links in an integrated circuit device. U.S. Pat. No. 4,758,863 to Nikkel illustrates a multilevel reticle having multiple masks of integrated circuit patterns. U.S. Pat. No. 5,907,492 to Akram et al teaches a method for use in an integrated circuit manufacturing process. Data from repair procedures conducted at wafer probe is used to determine whether further repairs will be performed. This method uses a laser fuse identification code to track repair procedures performed.
A principal object of the present invention is to provide an effective method of detecting the presence of a reticle option layer in an integrated circuit device.
A further object of the present invention is to provide a method of detecting reticle option layers in an integrated circuit device by electrically measuring the performance of two MOS transistors where the electrical performance of one transistor is affected by the presence of the reticle option while the other transistor is a standard, or control device.
A yet further object of the present invention is to provide a method of detecting reticle option layers where the reticle option layer is a threshold implantation.
Another further object of the present invention is to provide a method of detecting reticle option layers by directly probing the integrated circuit die.
Another further object of the present invention is to provide a reticle detection method for use with either NMOS or PMOS transistors.
Another further object of the present invention is to provide a method of detecting reticle option layers by probing the pins of the packaged integrated circuit.
Another yet further object of the present invention is to detect reticle option layers by probing the pins of the packaged circuit where a selection and amplification circuit facilitates access to the MOS transistors from the package pins.
Another still further object of the present invention is to detect reticle option layers by probing the pins of the packaged circuit where a selection and amplification circuit facilitates access to the MOS transistors from the package pins where either NMOS or PMOS transistors are sensed.
In accordance with the objects of this invention, a new method of detecting a threshold voltage implantation reticle option layer in an integrated circuit device has been achieved. The current through a first MOS transistor in an integrated circuit device is measured by forcing a test voltage on the drain and the gate. The gate and the drain of the first MOS transistor are connected together while the source of the first MOS transistor is connected to a reference voltage. The first MOS transistor has the standard threshold voltage implantation but not the threshold voltage implantation reticle option layer. The current through a second MOS transistor in the integrated circuit device is measured by forcing the same test voltage on the drain and the gate. The gate and the drain of the second MOS transistor are connected together while the source of the second MOS transistor is connected to the same reference voltage. The second MOS transistor has both the standard threshold voltage implantation and the threshold voltage implantation reticle option layer. The current through the first MOS transistor and the current through the second MOS transistor are compared to detect the presence of the threshold voltage implantation reticle option layer in the integrated circuit device. The method may be used for either NMOS or PMOS transistors.
Also in accordance with the objects of this invention, a new method of detecting a threshold voltage implantation reticle option layer in an integrated circuit device has been achieved. A first NMOS transistor in an integrated circuit device is selected in a first test mode so that the voltage at the drain and the gate of the first NMOS transistor may be measured at an output pin of the integrated circuit device. The gate and the drain of the first NMOS transistor are connected together. The first NMOS transistor has the standard threshold voltage implantation but not the threshold voltage implantation reticle option layer. The voltage at the output pin in the first test mode is measured when an internal standard voltage is connected to the drain and the gate through an internal standard resistance while the source of the first NMOS transistor is connected to ground. A second NMOS transistor in the integrated circuit device is selected in a second test mode so that the voltage at the drain and the gate of the second NMOS transistor may be measured at the output pin of the integrated circuit device. The gate and the drain of the second NMOS transistor are connected together. The second NMOS transistor has both the standard threshold voltage implantation and the threshold voltage implantation reticle option layer. The voltage at the output pin in the second test mode is measured when the internal standard voltage is connected to the drain and the gate through the internal standard resistance while the source of the NMOS transistor is connected to ground. The voltage at the output pin in the first test mode is compared with the voltage at the output pin in the second test mode to detect the presence of the threshold voltage implantation reticle option layer in the integrated circuit device.
Also in accordance with the objects of this invention, a new method of detecting a threshold voltage implantation reticle option layer in an integrated circuit device has been achieved. A first PMOS transistor in an integrated circuit device is selected in a first test mode so that the voltage at the drain and the gate of the first PMOS transistor may be measured at an output pin of the integrated circuit device. The gate and the drain of the first PMOS transistor are connected together. The first PMOS transistor has the standard threshold voltage implantation but not the threshold voltage implantation reticle option layer. The voltage at the output pin in the first test mode is measured when an internal standard voltage is connected to the source while the drain and the gate are connected to ground through an internal standard resistance. A second PMOS transistor in the integrated circuit device is selected in a second test mode so that the voltage at the drain and the gate of the second PMOS transistor may be measured at the output pin of the integrated circuit device. The gate and the drain of the second PMOS transistor are connected together. The second PMOS transistor has both the standard threshold voltage implantation and the threshold voltage implantation reticle option layer. The voltage at the output pin in the second test mode is measured when the internal standard voltage is connected to the source while the drain and the gate are connected to ground through the internal standard resistance. The voltage at the output pin in the first test mode is compared with the voltage at the output pin in the second test mode to detect the presence of the threshold voltage implantation reticle option layer in the integrated circuit device.